The present invention relates generally to integrated circuit (IC) designs, and more particularly to a bias monitoring circuit design.
In a complicated IC, such as system-on-chip (SOC), internal bias voltage often needs to be monitored through an external pad. FIG. 1 is a schematic diagram illustrating a conventional bias voltage monitoring circuit 100, which comprises a pad 102 coupled to a node 106 where the bias voltage is applied. Then the bias voltage level may be monitored at the pad 102. As an external pad on an IC package, the pad 102 needs to be protected by an ESD protection circuit 110, which comprises a resistor 113, a P-type metal-oxide-semiconductor (PMOS) transistor 122, an N-type metal-oxide-semiconductor (NMOS) transistor 124 and diodes 132 and 134. The resistor 113 is coupled between the node 106 and the pad 102. The PMOS transistor 122 has a gate and source coupled to a positive high voltage supply (VDD) and a drain coupled to the pad 102. The NMOS transistor 124 has a gate and source coupled to a complementary low voltage supply, or ground (GND) and a drain coupled to the pad 102. The transistors 122 and 124 essentially serve as reverse biased transistor diodes. The diodes 132 and 134 may be formed by PN junctions. The diode 132, coupled between the VDD and the pad 102, is also reversely biased, so is the diode 134, which is coupled between the GND and the pad 102. These reverse biased ESD protection devices 122, 124, 132 and 134 are supposed to be off during normal operations, and discharge current only during an ESD event. However, if the bias node 106 turned to a negative voltage lower than the GND, then both the NMOS transistor 124 and the diode 134 may be turned on and causing current leakages through the devices 124 and 134.
As such, what is desired is a bias monitoring circuit that can monitor both positive and negative biases without causing leakage current.